The present invention relates to a semiconductor package, and more particularly, but not exclusively, to a pin-grid-array package (hereinafter abbreviated as a PGA package) including a substrate provided on one surface with a plurality of terminal or connector pins.
A typical conventional PGA semiconductor package is shown in FIGS. 3(a) and 3(b). The illustrated PGA package includes a semiconductor element 102 in the form of a quad flat package (hereinafter simply referred to as a QFP) or a packaged semiconductor chip of a quadrate or rectangular configuration mounted on a surface of a rectangular-shaped substrate 101, the QFP 102 having a multitude of terminals 103 outwardly extending from the outer peripheral side edges thereof. The terminals 103 are connected by soldering to corresponding conductive connector lands 104 which are formed on the substrate 101 in an aligned parallel relation with the four side edges thereof at locations spaced apart a predetermined distance. The connector lands 104 are electrically connected through fine connecting wires 105, such as gold wires, to corresponding external terminals 106 in the form of connector pins which are disposed around the QFP 102 and which vertically extend from the other surface of the substrate 101. The respective connector pins 106 have their basal ends inserted into and fixedly secured, such as by soldering to corresponding through-holes (not shown) which are perforated through the substrate 101 and disposed in a grid-like pattern.
With the above-described conventional PGA package, however, the number of connector pins 106 is relatively limited and the distance or pitch between adjacent pins 106 is relatively wide, so the number of connecting wires 105 passing between adjacent connector pins 106 particularly near the corners of the QFP 102 is relatively limited, thus giving rise to no problem or difficulty in wiring. However, as the number of the connector pins 106 increases, the following problems arise.
In the course of recent developments in semiconductor technology, the increased number of the connector pins 106 as well as the resultant reduced distance or pitch between adjacent pins 106 inevitably leads to an increase in wiring density of the connecting wires 105. As a result, the number of the connecting wires 105 disposed between adjacent pins 106 at locations near the corners of the QFP 102 is greatly increased (e.g., nearly doubled) as compared with the other portions thereof, thus making it extremely difficult to achieve proper wire arrangements particularly at locations near the corners of the QFP 102.